Embedded programs are \u201cbare metal\u201d programs, i.e. without an underlying operating system (OS). You have full control over the hardware of embedded systems. You also have full responsibility, no convenient functions are available.<\/p>\n\n\n\n
(2) Retrace Build Steps<\/h3>\n\n\n\n
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Cross Compiler<\/li>\n<\/ul>\n\n\n\n
arm-non-eabi-gcc<\/code> compiles header files, libraries and main.c and generate *.o<\/code> files. -I<\/code> options are for specifying directories to search for header files to be included. Here the device header XMC4500.h are the header files for the GPIO driver.<\/p>\n\n\n\n
*.o<\/code> files are compiled but unlinked versions of source files, not human-readable.<\/p>\n\n\n\n
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Cross Linker<\/li>\n<\/ul>\n\n\n\n
arm-non-eabi-gcc<\/code> links all *.o<\/code> files into main.elf<\/code> file. -T<\/code> option gives the linker description file *.ld<\/code>. <\/p>\n\n\n\n
*.elf<\/code> files (executable<\/strong> and linkable<\/strong> format) are compiled and linked programs, ready to execute on the architecture they are built for. <\/p>\n\n\n\n
That means, ELF<\/code> format is used in two ways: The linker<\/strong> reads it as an input that can be linked with other objects. The loader<\/strong> interprets it as an executable program. <\/p>\n\n\n\n
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Important ELF sections<\/p>\n\n\n
\n<\/figure><\/div><\/blockquote>\n\n\n\n
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objcopy<\/li>\n<\/ul>\n\n\n\n
arm-non-eabi-objcopy<\/code> creates *.hex<\/code> files, which is pure machine code together with information about instruction addresses, technically human-readable.<\/p>\n\n\n\n
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objdump<\/li>\n<\/ul>\n\n\n\n
arm-non-eabi-objdump<\/code> creates *.lst<\/code> files, which is a human-readable copy of parts of the *.elf<\/code> file. What to put here is assigned by options of objdump<\/code>, but usually it is:<\/p>\n\n\n\n
– Section headers (where .data, .bss, etc. are located and how large they are)<\/p>\n\n\n\n
– Disassembly of the .text section interleaved with the C instructions it was compiled from. (.text\u90e8\u5206\u7684\u53cd\u6c47\u7f16\u4ee5\u53ca\u5bf9\u5e94\u7684\u7684C\u6307\u4ee4)<\/p>\n\n\n\n
(3) Difference from Computer Programs<\/h3>\n\n\n\n
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Cross-compiler instead of compiler<\/li>\n\n\n\n
Device<\/strong> header and device linker file needed<\/li>\n\n\n\n
Often additional libraries<\/strong> and drivers necessary<\/li>\n\n\n\n
Programming onto uC as another final step<\/li>\n<\/ul>\n\n\n\n\n\n\n\n
2. XMC4500 Board<\/h2>\n\n\n\n
(1) Functional Blocks<\/h3>\n\n\n\n
CPU, memory, clock and reset, timers\/counters, communications, analogs, GPIOs<\/p>\n\n\n
\n<\/figure><\/div>\n\n\n
(2) Peripherals<\/h3>\n\n\n\n
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CCU4<\/li>\n<\/ul>\n\n\n\n
provides several counters for PWM generation, counting external events<\/p>\n\n\n\n
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ADC <\/li>\n<\/ul>\n\n\n\n
Measures analog signals<\/p>\n\n\n\n
<\/p>\n\n\n\n
(3) Accessing Peripherals<\/h3>\n\n\n\n
Memory-mapped<\/strong>: I\/O devices are accessed through memory addresses, just like normal memory, the processor can access them by reading or writing to those memory addresses. It is generally more flexible and easier to use, as it allows the processor to access I\/O devices using the same instructions and addressing modes as it uses for normal memory. BUT the memory bus has to connect to each and every peripheral, whereas a longer bus reduces the maximal clock frequency, especially when going off-chip.<\/p>\n\n\n\n
Port-mapped: I\/O devices are accessed through dedicated I\/O ports, each I\/O device is assigned a unique port address, and the processor can access the device by reading or writing to that port address via special instructions IN<\/code>, OUT<\/code> instead of LD<\/code>, ST<\/code>. It is generally faster and more efficient than memory mapped I\/O, as it requires fewer bus transactions and can be implemented using a simpler addressing scheme. BUT specialized instructions and addressing modes are needed for different devices, which leads to additional complexity.<\/p>\n\n\n
\n<\/figure><\/div>\n\n\n
<\/p>\n\n\n\n
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3. Cortex M4<\/h2>\n\n\n\n
(1) Functional Blocks<\/h3>\n\n\n\n
The Cortex-M4 has a three-stage pipeline (Fetch, Decode, Execute) with the following functional blocks.<\/p>\n\n\n
\n<\/figure><\/div>\n\n\n
(2) Registers<\/h3>\n\n\n\n
1. Registers for Function Arguments<\/h4>\n\n\n
\nR1:R0<\/strong> for the return value<\/figcaption><\/figure><\/div>\n\n\n
2. Caller\/Callee-saved Registers<\/h4>\n\n\n\n
\n
Registers are special memory locations in the processor that are used to store data temporarily while a program is running.<\/p>\n\n\n\n
Caller-saved registers (R0 – R3, R12<\/strong>) are registers that are expected to be preserved by a called function. This means that the calling function (the “caller”) is responsible for saving the values of these registers before making the function call, and restoring them after the function returns.<\/p>\n\n\n\n
Callee-saved registers (R4 – R11<\/strong>), on the other hand, are registers that are expected to be preserved by the called function, and are guaranteed to retain their values after the function returns. This means that the called function (the “callee”) is responsible for saving the values of these registers before modifying them, and restoring them before returning control to the calling function. To do this, the callee must either leave them unchanged or push them on the stack in the beginning and pop them back before return.<\/p>\n<\/blockquote>\n\n\n\n
3. Special Registers<\/h4>\n\n\n\n
Register R13 – R15 are not classified as caller- or callee-saved. <\/p>\n\n\n\n
R13 (Stack Pointer): The SP<\/code> determines the border between allocated and unallocated memory on the stack. If a function requires stack space, it allocates it by decreasing the SP<\/code>.<\/p>\n\n\n\n
R14 (Link Register): The LR<\/code> can be seen as a kind of hidden argument register that tells a callee the return address.<\/p>\n\n\n\n
R15 (Program Counter)<\/p>\n\n\n\n
4. PSR (Program status registers)<\/h4>\n\n\n\n
ApplicationPSR: N, Z, C, V (flags)<\/p>\n\n\n\n
ExecutionPSR: IT (if-then instruction status bits), T (thumb state, always 1 for Cortex-M)<\/p>\n\n\n\n
InterruptPSR: EN (exception number)<\/p>\n\n\n\n
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4. Assembler<\/h2>\n\n\n\n
(1) Instructions<\/h3>\n\n\n\n
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Data Processing<\/li>\n<\/ul>\n\n\n\n
ADD r3, r4, r5; <\/code><\/p>\n\n\n\n
Add the contents of r4<\/code> and r5<\/code> and store the result in r3<\/code>.<\/p>\n\n\n\n
ADC r0, r1, r2; <\/code><\/p>\n\n\n\n
Add the contents of r1<\/code> and r2<\/code> and store the result in r0<\/code>, taking into account the carry flag.<\/p>\n\n\n\n
SUB r3, r4, r5;<\/code><\/p>\n\n\n\n
Subtract the contents of r5<\/code> from r4<\/code> and store the result in r3<\/code>.<\/p>\n\n\n\n
NEG r12, r13;<\/code><\/p>\n\n\n\n
Negate the contents of r13<\/code> and store the result in r12<\/code>.<\/p>\n\n\n\n
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Data Move<\/li>\n<\/ul>\n\n\n\n
MOV r0, #0; <\/code><\/p>\n\n\n\n
Move the value 0<\/code> into register r0<\/code>. The #<\/code> symbol indicates that the value is an immediate value, rather than a register or memory location.<\/p>\n\n\n\n
LDR r1, [r2]; <\/code><\/p>\n\n\n\n
Load the value at the memory location pointed to by r2<\/code> into r1<\/code>. The []<\/code> symbol indicates that the operand is a memory location<\/strong>, rather than a register or immediate value.<\/p>\n\n\n\n
STR r6, [r7, #4];<\/code> <\/p>\n\n\n\n
Store the contents of r6<\/code> at the memory location pointed to by r7 + 4<\/code>.<\/p>\n\n\n\n
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Control Flow<\/li>\n<\/ul>\n\n\n\n
B foo; <\/code><\/p>\n\n\n\n
Jump to the label foo<\/code>. This instruction adds a delta to the current PC.<\/p>\n\n\n\n
BX r0; <\/code><\/p>\n\n\n\n
Jump to the address stored in r0<\/code> and change the execution mode. This branch writes a new address value in the PC<\/p>\n\n\n\n
Call the function foo<\/code> and store the return address in the link register. Before branch execution PC is copied into the link register (LR).<\/p>\n\n\n\n
pop {r4,r5,r7,pc};<\/code> (function return<\/strong>)<\/p>\n\n\n\n
(2) RISC vs CISC<\/h3>\n\n\n\n
RISC: \u9664\u4e86load\/store\uff0c\u6ca1\u6709\u5176\u4ed6\u8bbf\u95ee\u5185\u5b58\u7684\u6307\u4ee4\u3002\u6307\u4ee4\u56fa\u5b9a\u957f\u5ea6\uff0c\u6307\u4ee4\u5f88\u591a\uff0c\u4f46CPU\u5f88\u7b80\u5355\uff0c\u65f6\u949f\u9891\u7387\u5f88\u9ad8\u3002By reducing the number of addressing modes, RISC computer achieves less complexity and higher clock frequencies<\/p>\n\n\n\n
Distinct load<\/code> and store<\/code> instructions, lacking memory addressing modes for data processing instructions (e.g. ADD), and fixed length instructions all indicate RISC.<\/p>\n\n\n\n
Use the LSB of PC<\/code> for detection. An even address is seen as an ARM code, and an odd address as Thumb.<\/p>\n\n\n\n
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Operands<\/li>\n<\/ul>\n\n\n\n
result<\/code> counts as an operand of the opcode, thus Cortex-M opcodes have three operands result, operand1, operand2<\/code><\/p>\n\n\n\n
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Suffix “S”<\/li>\n<\/ul>\n\n\n\n
Suffix “S” tells the CPU to update the conditional execution flags<\/strong> depending on the result of this operation, i.e. ADDS is ADD with S suffix, only ADDS updates APSR flags.<\/p>\n\n\n\n
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32-bit Literal<\/li>\n<\/ul>\n\n\n\n
As instructions are only 32-bit long and a few bits are needed to encode the opcode, the 32-bit literal cannot be placed as an immediate in the instruction. Use MOV<\/code> for the lower 16 bits and MOVT<\/code> for the upper 16 bits.<\/p>\n\n\n\n
Alternatively, we can use the so-called literal pool<\/strong> with LDR r0,=0x12345678<\/code>. The literal is placed into the text section right after the current function and is loaded from there using the PC<\/code> with an offset automatically calculated by the assembler.<\/p>\n\n\n\n
\n
Function call<\/li>\n<\/ul>\n\n\n\n
Function calls\/ Jumps are done using B<\/code> or BX<\/code>. Note that the LR<\/code> needs to be updated to the address of the next instruction after the function call. BL<\/code> or BLX<\/code> do that automatically.<\/p>\n\n\n\n\n\n\n\n
5. GNU Debugger<\/h2>\n\n\n\n
(1) Comparisons of Debug Methods<\/h3>\n\n\n
\n<\/figure><\/div>\n\n
\n<\/figure><\/div>\n\n\n
(2) GDB Overview<\/h3>\n\n\n\n
GDB can be directly attached to any PC program. <\/p>\n\n\n
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<\/p>\n\n\n\n